Introduction

Understanding and debugging syntax errors thrown by Verilog compilers (and other fun stuff).

This is a guide to writing and debugging Verilog code. It is primarily intended to help students of EECS 270: Intro to Digital Logic at the University of Michigan, but might be useful to other Verilog programmers as well.

It covers some basics of Verilog, suggestions on designing good hardware, as well as navigating a slew of errors and warnings generated (or even worse, ignored) by the Verilog compiler/synthesizer.

(Note: I sometimes use compiler/synthesiser interchangeably. They are different—compiler prepares a simulation executable, a synthesiser prepares netlists and describes hardware connections. However, for the most part of EECS 270, this distinction isn't too important.

A lot of commonly faced issues arise from approaching Verilog from a software engineering perspective. Verilog is a hardware description language—similarities in syntax with software programming languages should not be confused for semantic equivalence. These notes discuss some of these differences.

I hope these notes are helpful. Feel free to reach out to me ([e-mail]) if you have any questions or suggestions.